Integrated circuits are an integral part of any electronic device. A variety of integrated circuits are often used together to enable the operation of the electronic device. While integrated circuits are typically designed for a particular application, one type of integrated circuit which enables flexibility is a programmable logic device (PLD). A PLD is designed to be user-programmable so that users may implement logic designs of their choices. One type of PLD is the Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” having a two-level AND/OR structure connected together and to input/output (I/O) resources by an interconnect switch matrix. Another type of PLD is a field programmable gate array (FPGA). In a typical FPGA, an array of configurable logic blocks (CLBs) is coupled to programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a hierarchy of programmable routing resources according to a routing configuration. For both of these types of programmable logic devices, the functionality of the device is controlled by configuration data bits of a configuration bitstream provided to the device for that purpose. The configuration data bits may be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
PLDs typically exhibit greater static power consumption than dedicated logic devices such as application specific integrated circuits (ASICs). One reason for the PLD's high power consumption is because only a subset of the available resources of a PLD may be used for any given design, and the unused resources still consume static power. That is, while the unused resources are necessary for providing greater mapping flexibility to the PLD, these unused resources still consume static power in the form of leakage current. PLDs also have a significantly higher dynamic power consumption than standard ASICs having dedicated logic because of the hardware overhead required to make PLDs programmable by the end-user.
Accordingly, there is a need for reducing the power consumed by circuits such as programmable logic devices.